View 534AF622M080BG_2431671.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary rev. 0.3 4/06 copyright ? 2006 by silicon laboratories si550 this information applies to a product under dev elopment. its characteristics and specifications are s ubject to change without n otice. si550 v oltage -c ontrolled c rystal o scillator (vcxo) 10 mh z to 1.4 gh z features applications description the si550 vcxo utilizes silicon laboratories? advanced dspll ? circuitry to provide a low-jitter clock at high fre quencies. the si550 is available with any-rate output frequency from 10 to 945 mhz and selected frequencies to 1400 mhz. unlike traditional vcxo?s where a different crystal is required for each output frequency, the si550 uses one fixed crystal to provide a wide range of output frequencies. this ic based approach allows the crystal resonator to provide exceptional frequency stability and reliability. in addition, dspll clock synthesis provid es superior supply noise rejection, simplifying the task of generating low-jitter clocks in noisy environments typically found in communication systems. the si550 ic-based vcxo is factory configurable for a wide variety of user specifications, including frequency, supply voltage, output format, tuning slope, and temperature stability. specific configurations are factory programmed at time of shipment, thereby eliminating long lead times associated with custom oscillators. functional block diagram available with any-rate output frequencies from 10 mhz to 945 mhz and selected frequencies to 1.4 ghz 3rd generation dspll ? with superior jitter performance 3x better frequency stability than saw based oscillators internal fixed crystal frequency ensures high reliability and low aging available cmos, lvpecl, lvds, & cml outputs 3.3, 2.5, and 1.8 v supply options industry-standard 5 x 7 mm package and pinout lead-free/rohs-compliant sonet / sdh xdsl 10 gbe lan / wan low-jitter clock generation optical modules clock and data recovery fixed frequency xo any-rate 10-1400 mhz dspll ? clock synthesis adc v dd clk+ clk? vc oe gnd ordering information: see page 8. pin assignments: see page 7. (top view) si5602 1 2 3 6 5 4 v c gnd oe v dd clk+ clk? p reliminary d ata s heet
si550 2 preliminary rev. 0.3 1. electrical specifications table 1. recommended operating conditions parameter symbol test condition min typ max units supply voltage 1 v dd 3.3 v option 2.97 3.3 3.63 v 2.5 v option 2.25 2.5 2.75 1.8 v option 1.71 1.8 1.89 supply current i dd output enabled ? 90 ? ma tristate mode ? 60 ? output enable (oe) 2 v ih 0.75 x v dd ?? v v il ??0.5 operating temperature range t a ?40 ? 85 oc notes: 1. selectable parameter specified by part number. see section 3. "ordering information" on page 8 for further details. 2. oe pin includes a 17 k ? pullup resistor to vdd. pulling oe to ground causes outputs to tristate. table 2. v c control voltage input parameter symbol test condition min typ max units control voltage tuning slope 1,2,3 k v 10 to 90% of v dd ?45 90 135 180 ?ppm/v control voltage linearity 4 l vc bsl ?5 1 +5 % incremental ?10 5 +10 modulation bandwidth bw 9.3 10.0 10.7 khz v c input impedance z vc 500 ? ? k ? nominal control voltage v cnom @ f o ?3/8xv dd ?v control voltage tuning range v c 0v dd v notes: 1. positive slope; selectable option by part number . see section 3. "ordering information" on page 8. 2. for best jitter and phase noise performance, always choose the smallest k v that meets the application?s minimum apr requirements. see ?an266: vcxo tuning slope (k v ), stability, and absolute pull r ange (apr)? for mo re information. 3. k v variation is 28% of typical values. 4. bsl determined from deviation from best straight line fit with v c ranging from 10 to 90% of v dd . incremental slope determined with v c ranging from 10 to 90% of v dd .
si550 preliminary rev. 0.3 3 table 3. clk output frequency characteristics parameter symbol test condition min typ max units nominal frequency 1,2,3 f o lvds/cml/lvpecl 10 ? 945 mhz cmos 10 ? 160 temperature stability 1,4 ? f/f o t a = ?40 to +85 oc ?20 ?50 ?100 ? ? ? +20 +50 +100 ppm absolute pull range 1,4 apr 25 ? 150 ppm aging frequency drift over 15 year life. ??10ppm power up time 5 t osc ??10ms notes: 1. see section 3. "ordering information" on page 8 for further details. 2. specified at time of order by part number. also available in frequencies from 970 to 1134 mhz and 1213 to 1417 mhz. 3. nominal output frequency set by v cnom =3/8xv dd . 4. selectable parameter specified by part number. 5. time from power up or tristate mode to f o . table 4. clk output levels and symmetry parameter symbol test condition min typ max units lvpecl output option 1 v o mid-level v dd ? 1.42 ? v dd ? 1.25 v v od swing (diff) 1.1 ? 1.9 v pp v se swing (single-ended) 0.5 ? 0.93 v pp lvds output option 2 v o mid-level 1.125 1.20 1.275 v v od swing (diff) 0.32 0.40 0.50 v pp cml output option 2 v o mid-level ? v dd ? 0.75 ? v v od swing (diff) 0.70 0.95 1.20 v pp cmos output option 3 v oh i oh =32ma 0.8 x v dd ? v dd v v ol i ol =32ma ?? 0.4 rise/fall time (20/80%) t r, t f lvpecl/lvds/cml ? ? 350 ps cmos with cl = 15 pf ? 1 ? ns
si550 4 preliminary rev. 0.3 symmetry (duty cycle) sym lvpecl: v dd ? 1.3 v (diff) lvds: 1.25 v (diff) cmos: v dd /2 45 ? 55 % notes: 1. 50 ? to v dd ? 2.0 v. 2. r term = 100 ? (differential). 3. c l = 15 pf table 5. clk output phase jitter parameter symbol test condition min typ max units phase jitter (rms) 1,2,3 for f out > 500 mhz j kv = 45 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.35 0.38 ? ? ps kv = 90 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.43 0.41 ? ? kv = 135 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.52 0.46 ? ? kv = 180 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.64 0.52 ? ? phase jitter (rms) 1,2,3 for f out of 125 to 500 mhz j kv = 45 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.42 0.58 ? ? ps kv = 90 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.48 0.60 ? ? kv = 135 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.57 0.64 ? ? kv = 180 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.67 0.68 ? ? notes: 1. differential modes: lvpecl/lvds/cml. refer to an255, an256, and an266 for further information. 2. for best jitter and phase noise performance, always choose the smallest k v that meets the application?s minimum apr requirements. see ?an266: vcxo tuning slope (k v ), stability, and absolute pull r ange (apr)? for mo re information. 3. see ?an255: replacing 622 mhz vcso devices with the si550 vcxo? for comparison highlighting power supply rejection (psr) advantage of si55x versus saw-based solutions. table 4. clk output levels and symmetry (continued) parameter symbol test condition min typ max units
si550 preliminary rev. 0.3 5 table 6. clk output period jitter parameter symbol test condition min typ max units period jitter* for f out < 160 mhz j per rms ? 2 ? ps peak-to-peak ? 14 ? *note: any output mode, incl uding cmos, lvpecl, lvds, cml. n = 1000 cycles. table 7. clk output phase noise (typical) configuration f c k v output 74.25 mhz 45 ppm/v cmos 300 mhz 90 ppm/v lvpecl 622.08 mhz 45 ppm/v lvpecl units offest frequency (f) 100 hz 1khz 10 khz 100 khz 1mhz 10 mhz 100 mhz l (f) dbc/hz ?94 ?117 ?128 ?135 ?138 ?143 n/a ?74 ?98 ?112 ?122 ?134 ?144 ?147 ?77 ?101 ?114 ?118 ?128 ?144 ?147
si550 6 preliminary rev. 0.3 table 8. absolute maximum ratings parameter symbol rating units supply voltage v dd ?0.5 to +3.8 volts input voltage v i ?0.5 to v dd + 0.3 volts storage temperature t s ?55 to +125 oc esd sensitivity (hbm, per jesd22-a114) esd >2500 volts soldering temperature (lead-free profile) t peak 260 oc soldering temperature time @ t peak (lead-free profile) t p 10 seconds note: stresses beyond those listed in absolute maximum ratings may cause permanent damage to the device. functional operation or specification compliance is not implied at these conditions. table 9. environmental compliance the si550 meets the following qualification test requirements. parameter conditions/ test method mechanical shock mil-std-883f, method 2002.3 b mechanical vibration mil-std-883f, method 2007.3 a solderability mil-std-8 83f, method 203.8 gross & fine leak mil-std-883f, method 1014.7 resistance to solvents mil-std-883f, method 2016
si550 preliminary rev. 0.3 7 2. pin descriptions table 10. si550 pin descriptions pin name type function 1 v c analog input control voltage 2 oe* input output enable: 0 = clock output disabled (outputs tri-stated) 1 = clock output enabled 3 gnd ground electrical and case ground 4 clk+ output oscillator output 5 clk? (n/a for cmos) output complementary output (n/c for cmos) 6 v dd power power supply voltage *note: oe includes 17 k ? pullup resistor to v dd . 1 2 3 6 5 4 v c gnd oe v dd clk+ clk? (top view)
si550 8 preliminary rev. 0.3 3. ordering information the si550 was designed to support a variety of options including frequency , temperature stabilit y, tuning slope, output format, and v dd . specific device configurations are prog rammed into the si550 at time of shipment. configurations are specified using the part number configuration chart shown below. silicon labs provides a web browser-based part number configuration utility to simplify this process. refer to www.silabs.com/ vcxopartnumber to access this tool and for further or dering instructions. the si550 vcxo series is supplied in an industry-standard, rohs compliant, lead-free, 6- pad, 5 x 7 mm package. tape and reel packaging is an ordering option. example part number: 550af622m080bgr is a 5 x 7 mm vcxo in a 6 pad package. the nominal frequency is 622.080 mhz, with a 3.3 v supply and lvpecl output . temperature stability is specified as 50 pp m and the tuning slope is 135 ppm/v. the part i s specified for a ?40 to +85 c ambient temperature r ange operation and is shipped in tape and reel format. dd r = tape & reel blank = trays operating temp range (c) g ?40 to +85 c device revision letter 2 nd option code temperature tuning slope minimum apr stability kv (ppm) code ppm (max) ppm/v (typ) @ 3.3 v @ 2.5 v @ 1.8 v a 100 180 100 75 25 b 100 90 30 note 6 note 6 c 50 180 150 125 75 d50 90 803025 e 20 45 25 note 6 note 6 f 50 135 100 75 50 notes: 1. for best jitter and phase noise performance, always choose the smallest kv that meets the application?s minimum apr requirements. unlike saw-based solutions which require higher higher kv values to account for their higher temperature dependence, the si55x series provides lower kv options to minimize noise coupling and jitter in real-world pll designs. see an255 and an266 for more information. 2. apr is the ability of a vcxo to track a signal over the product lifetime. a vcxo with an apr of 25 ppm is able to lock to a clock with a 25 ppm stability, over 15 years. 3. nominal pull range () = 0.5 x v dd x tuning slope. 4. nominal absolute pull range ( apr) = pull range ? stability ? lifetime aging = 0.5 x v dd x tuning slope ? stability ? 10 ppm 5. minimum apr values noted above include worst case values for all parameters. 6. combination not available. 550 vcxo product family 1 st option code code vdd output format a3.3lvpecl b3.3lvds c3.3cmos d3.3cml e2.5lvpecl f2.5lvds g2.5cmos h2.5cml j1.8cmos k1.8cml notes : cmos available to 160 mhz. frequency (e.g. 622m080 is 622.080 mhz) available frequency range is 10 to 945 mhz, 970 to 1134, and 1213 to 1417 mhz. the position of ?m? shifts to denote higher or lower frequencies. 550 x x xxxmxxx b g r
si550 preliminary rev. 0.3 9 4. outline diagram and suggested pad layout figure 1 illustrates the package details for the si550. table 11 lists the valu es for the dimensions shown in the illustration. figure 1. si550 outline diagram table 11. package diagram dimensions (mm) dimension min nom max a 1.45 1.65 1.85 b1.21.41.6 c0.60 typ. d 7.00 bsc. d1 6.10 6.2 6.30 e 2.54 bsc. e 5.00 bsc. e1 4.30 4.40 4.50 l 1.07 1.27 1.47 s 1.815 bsc. r 0.7 ref. aaa ? ? 0.15 bbb ? ? 0.15 ccc ? ? 0.10 ddd ? ? 0.10
si550 10 preliminary rev. 0.3 5. 6-pin pcb land pattern figure 2 illustrates the 6-pin pcb land pa ttern for the si550. table 12 lists th e values for the dimensions shown in the illustration. figure 2. si550 pcb land pattern table 12. pcb land pattern dimensions (mm) dimension min max d2 5.08 ref e 2.54 bsc e2 4.15 ref gd 0.84 ? ge 2.00 ? vd 8.20 ref ve 7.30 ref x1.70 typ y2.15 ref zd ? 6.78 ze ? 6.30 notes: 1. dimensioning and tolerancing per the ansi y14.5m-1994 specification. 2. land pattern design based on ipc-7351 guidelines. 3. all dimensions shown are at ma ximum material condition (mmc). 4. controlling dimension is in millimeters (mm).
si550 preliminary rev. 0.3 11 d ocument c hange l ist revision 0.2 to revision 0.3 updated 1. "electrical sp ecifications" on page 2. updated ordering and format of table 1 through table 9. updated lvds and cml in table 4, ?clk output levels and symmetry,? on page 3. updated rms jitter values in table 5, ?clk output phase jitter,? on page 4. added typical phase noise performance data in table 5, ?clk output phase jitter,? on page 4. updated 3. "ordering information" on page 8. removed ordering option e at v dd = 2.5 v in table for the 2nd option code. typical aprs replaced with minimum apr values. new 135 ppm/v k v option included.
si550 12 preliminary rev. 0.3 c ontact i nformation silicon laboratories inc. 4635 boston lane austin, tx 78735 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: vcxoinfo@silabs.com internet: www.silabs.com silicon laboratories, silicon labs, and dspll are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

▲Up To Search▲

Price & Availability of 534AF622M080BG

	To Download 534AF622M080BG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .